Communication semiconductor integrated circuit device and wireless communication system

ABSTRACT

The invention provides a communication semiconductor integrated circuit device (RF IC) capable of pulling in the frequency of a PLL circuit to a desired set frequency at high speed even in the case where a frequency settable range of the PLL circuit is wide without providing a current source other than a current source for charging and discharging in an normal operation. An oscillator as a component of a PLL circuit is constructed so as to be operative in a plurality of bands. In a state where a control voltage of the oscillator is fixed to a predetermined value, an oscillation frequency of the oscillator is measured in each of bands and stored in a storing circuit. A set value for designating a band supplied at the time of PLL operation is compared with the stored measured frequency value. From a result of comparison, a band to be actually used in the oscillator is determined, and a frequency difference between the maximum frequency of the selected band and the set frequency is obtained. Further, a control voltage closest to the set frequency is determined on the basis of the frequency difference and the frequency variable range of the selected band and the control voltage is applied to the oscillator to start oscillating operation. After that, a PLL loop is closed and locked.

BACKGROUND OF THE INVENTION

The present invention relates to a technique effective to be applied toa PLL (Phase Locked Loop) circuit having a VCO (Voltage ControlledOscillator) and capable of switching an oscillation frequency andfurther to a high-speed pull-in technique of a PLL circuit. Moreparticularly, the invention relates to a technique effective to beapplied to a PLL circuit for generating an oscillation signal of apredetermined frequency mixed with a reception signal or transmissionsignal in a radio communication device such as a portable telephonecapable of transmitting/receiving signals in a plurality of bands, asemiconductor integrated circuit device for high frequencies having thesame, and a radio communication system.

In a radio communication system such as a portable telephone, a PLLcircuit is used as a local oscillator for generating an oscillationsignal of a predetermined frequency mixed with a reception signal ortransmission signal. Hitherto, there is a dual-band portable telephonecapable of handling signals in two frequency bands of, for example, GSM(Global System for Mobile Communication) of a band from 880 to 915 MHzand a DCS (Digital Cellular System) of a band from 1710 to 1785 MHz.Some dual-band portable telephones can deal with two bands by a singlePLL by switching the frequency of the PLL circuit.

In recent years, there is a demand for a triple-band portable telephonecapable of handling signals of, in addition to the GSM and DCS, a PCS(Personal Communication System) of a band from 1850 to 1915 MHz. It isexpected that a portable telephone capable of handling the larger numberof bands will be requested in future.

For such a semiconductor integrated circuit device for high frequencies(hereinbelow, called RF IC) for modulating a transmission signal anddemodulating a reception signal, which is used for a portable telephoneadapted to a plurality of bands, a direct conversion method is effectivefrom the viewpoint of reduction in the number of components. Althoughthe direct conversion method is relatively easily adapted to a pluralityof bands, the frequency range in which a VCO can oscillates is wide. Ifone VCO is used to cover the whole frequencies, the sensitivity of thecontrol voltage of the VCO becomes high and it causes a problem suchthat the VCO becomes vulnerable to external noise and fluctuations in apower source voltage.

On the other hand, to reduce the number of components, it is effectiveto form a VCO, which is conventionally generally provided as a moduleseparate from an RF IC, on the same semiconductor chip on which the RFIC is also mounted. However, in the case of forming a on-chip VCO,variations in the absolute value of an oscillation frequency increasefor the reason of manufacture, so that the function of adjusting theoscillation frequency after manufacture becomes indispensable. In thecase of adjusting the variations by trimming of general mask option orbonding wire option used for a conventional semiconductor integratedcircuit, increase in cost cannot be avoided.

SUMMARY OF THE INVENTION

The inventors et al. have developed and filed a communicationsemiconductor integrated circuit device (RF IC) having a PLL circuit(Japanese Unexamined Patent Publication No. 2002-11050: corresponding toPCT application No. GB2002/005152) in which sensitivity of a controlvoltage of a VCO does not become high even if the frequency range inwhich the VCO can oscillate is widened in order to be adapted to aplurality of bands and which is not easily influenced by external noiseand fluctuations in a power source voltage and can automatically correctvariations in oscillation frequency of the VCO by an internal circuit bythe following configuration. An oscillation circuit as a component ofthe PLL circuit is constructed so as to be operative in a plurality ofbands. In a state where a control voltage of the oscillation circuit isfixed to a predetermined value, an oscillation frequency of theoscillation circuit is measured in each of bands and stored in a storingcircuit. A set value for designating a band supplied in an operation ofthe PLL circuit is compared with the stored measured frequency value.From a result of comparison, a band to be actually used in theoscillation circuit is determined.

In a portable telephone, a frequency used is determined at the start oftransmitting/receiving operation, a VCO is started, and pull-in controlis performed so that a PLL circuit oscillates at the frequency. Thepull-in is desired to be performed in short time. In the publication,the pull-in control of the PLL circuit is not disclosed.

As a high-speed pull-in technique of a PLL circuit, for example, amethod of increasing current of a charge pump for charging a capacitorof a loop filter for generating a control voltage of a VCO at the startof pull-in is known. However, the pull-in method has problems such thata current source for increasing the current at the time of pull-in isnecessary in addition to a current source for charging/discharging acharge pump in normal operation. When the frequency settable range ofthe PLL circuit is wide, troublesome time control is necessary toaccurately pull the frequency of the PLL circuit into a desired setfrequency.

An object of the invention is to provide a communication semiconductorintegrated circuit device (RF IC) capable of pulling the frequency of aPLL circuit into a desired set frequency at high speed without providinga current source in addition to a current source forcharging/discharging in normal operation also in the case where afrequency settable range of the PLL circuit is wide.

Another object of the invention is to provide a communicationsemiconductor integrated circuit device capable of pulling in thefrequency of a PLL circuit into a desired set frequency accurately athigh speed even in the case where a frequency settable range of the PLLcircuit is wide.

Further another object of the invention is to provide a communicationsemiconductor integrated circuit device capable of performingcommunication with signals in a plurality of frequency bands andrealizing the reduced number of components by forming a VCO on the samesemiconductor chip.

The above and other objects and novel features will become apparent fromthe description of the specification and the accompanying drawings.

An outline of a representative invention in inventions disclosed in theapplication will be described as follows.

An oscillation circuit as a component of a PLL circuit is constructed soas to be operative in a plurality of bands. A circuit capable ofswitching a control voltage of the oscillation circuit to apredetermined direct-current voltage is provided. In a state where thecontrol voltage of the oscillation circuit is fixed to a predeterminedvalue, an oscillation frequency of the oscillation circuit is measuredin each of bands and stored in a storing circuit. A set value fordesignating a band supplied in an operation of the PLL circuit iscompared with the stored measured frequency value. From a result ofcomparison, a band to be actually used in the oscillation circuit isdetermined, and a frequency difference between the maximum frequency ofthe selected band and the set frequency is obtained. Further, a controlvoltage closest to the set frequency is determined on the basis of thefrequency difference and the frequency variable range of the selectedband and applied from the control voltage switching circuit to theoscillation circuit. After oscillating operation is started, a PLL loopis closed and locked.

According to the means, an initial voltage extremely close to thecontrol voltage applied when the oscillation circuit oscillates at adesired frequency can be applied at the start of oscillation operation.Thus, a communication semiconductor integrated circuit device having aPLL circuit capable of accurately performing pull-in at high speedwithout requiring a current source for pull-in of a PLL is obtained.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an embodiment of a PLL circuit towhich the invention is applied.

FIGS. 2A and 2B are graphs showing the relation between a controlvoltage Vc and an oscillation frequency fvco in the case where thefrequency variable range of a VCO is continuously changed in the PLLcircuit and the case where the frequency variable range is changed ineach of bands.

FIG. 3 is a flowchart showing an example of a frequency measuringprocedure of the VCO in the PLL circuit of the embodiment and a pull-inoperating procedure of the PLL circuit.

FIG. 4 is a diagram for explaining a method of determining a pull-ininitial voltage of the PLL circuit of the embodiment.

FIG. 5 is a configuration diagram showing a concrete example of apull-in initial voltage generating circuit as a component of the PLLcircuit of the embodiment.

FIG. 6 is a block diagram showing an example of the configuration of aradio communication system of a direct conversion method to which thePLL circuit according to the invention is applied.

FIG. 7 is a block diagram showing an example of the configuration of aradio communication system of a polar loop method to which the PLLcircuit according to the invention is applied.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the invention will be described hereinbelow withreference to the drawings.

FIG. 1 shows an example of a high-speed pull-in PLL circuit to which theinvention is applied. Shown in the diagram area VCO (Voltage ControlledOscillator) 10, a reference oscillation circuit (TCXO) 11 which uses acrystal oscillator and oscillates at precise high frequencies, avariable frequency divider 12 for dividing the frequency of anoscillation signal φvco of the VCO 10, a fixed frequency divider 13 fordividing the frequency of a reference oscillation signal φref of thereference oscillation circuit 11 to 1/65, a phase comparator 14 forcomparing the phase of a signal subjected to frequency division of thevariable frequency divider 12 with the phase of signal subjected tofrequency division of the fixed frequency divider 13 and outputting avoltage UP or DOWN according to a phase difference, a charge pump 15,and a loop filter 16. A PLL loop in which the capacitive element of theloop filter 16 is charged up by the charge pump 15, and the resultant isoutput as a control voltage Vc of the VCO (Voltage ControlledOscillator) 10 and the VCO 10 is oscillated at predetermined frequenciesis constructed.

The PLL circuit of the embodiment includes, as shown in FIG. 1: a switchSW0 provided between the charge pump 15 and the loop filter 16, capableof supplying a predetermined direct-current voltage VDC in place of avoltage Vc from the charge pump 15 at the time of frequency measurementor PLL pull-in; a pull-in initial voltage generating circuit 17 forgenerating the direct-current voltage VDC to be applied to the chargepump 15; the variable frequency divider 12 for calculating anoscillation signal of the VCO 10 and dividing the frequency; a storingcircuit 18 constructed by a register or the like for storing a valueobtained by calculation of the variable frequency divider 12; a banddetermining circuit 19 for comparing a frequency value stored in thestoring circuit 18 with set values N8 to N0 and A5 and A4 set from theoutside into the variable frequency divider 12 and generating bandswitch signals VB3 to VB0 of the VCO 10; and a control circuit 20 forcontrolling the switch SW0, variable frequency divider 12, storingcircuit 18, and band determining circuit 19.

At the time of measuring frequencies, the direct-current voltage VDCsupplied to the loop filter 16 by the switch SW0 may have any voltagevalue as long as it is within a valid variable range of the controlvoltage Vc. In the embodiment, the upper limit value (Vcp−max) of thevariable range of the control voltage Vc is selected. During measurementof frequencies, the direct-current voltage VDC is set to the same valuewhile the band is switched.

The VCO 10 takes the form of, for example, a Colpitts' oscillationcircuit using an LC resonance circuit. A plurality of capacitiveelements constructing the LC resonance circuit are provided in parallelvia switch elements. By selectively turning on the switch elements bythe band switch signals VB3 to VB0, the values of the capacitiveelements connected, that is, values of C of the LC resonance circuit areswitched, so that the oscillation frequency can be switched step bystep. On the other hand, the VCO 10 has a varicap diode as a variablecapacitive element. The capacitance value of the varicap diode ischanged by the control voltage Vc from the loop filter 16, and theoscillation frequency is continuously changed.

In the case of widening the frequency range to be covered by the VCO, ifit is realized only by changing the capacitance value of the varicapdiode by the control voltage Vc, a Vc−fvso characteristic becomes sharpas shown in FIG. 2A, the sensitivity of the VCO, that is, the ratio(Δf/ΔVc) between a frequency change amount and a control voltage changeamount increases and the VCO becomes vulnerable to noise. That is, onlywhen small noise occurs in the control voltage Vc, the oscillationfrequency fvco (φvco) of the VCO largely changes.

The VCO 10 of the embodiment is therefore constructed to performoscillation control according to a plurality of Vc−fvco characteristiclines as shown in FIG. 2B by providing a plurality of capacitiveelements constructing an LC resonance circuit in parallel and switchingthe capacitive elements used by the band switch signals VB3 to VB0 in nstages to change the value of C. Moreover, in this embodiment, byproviding the storing circuit 18 and band determining circuit 19, theadjusting work of adjusting frequencies performed in the conventionalPLL circuit becomes unnecessary.

Specifically, in the conventional PLL circuit, even in the case ofconstructing a VCO having a plurality of Vc−fvco characteristic lines asshown in FIG. 2B, the VCO is operated, frequencies are measured, and thefrequencies are adjusted so that each of the plurality of Vc−fvcocharacteristic lines has a predetermined initial value and apredetermined gradient. In contrast, in the PLL circuit of theembodiment, the switch SW0 is preliminarily switched to apply thepredetermined direct-current voltage VDC to the VCO 10, and thefrequency is measured in each of the bands and stored in the storingcircuit 18. In actual use, the set values N8 to N0 and A5 and A4according to a designated band given from the outside to the variablefrequency divider 12 are compared with measurement values stored in thestoring circuit 18. Only one of the plurality (n) of Vc−fvcocharacteristic lines, which can cover the frequency range of thedesignated band as shown in FIG. 2B is selected, and the VCO is switched(capacitive element is switched) so as to perform an oscillation controloperation according to the selected characteristic line.

According to such a method, by designing the VCO so as to cover a rangewhich is a little wider than the frequency range desired to be coveredby an amount corresponding to consideration of variations and so as tooverlap the frequency ranges of which neighboring Vc−fvco characteristiclines in the n stages by a small amount (desirably, the half) as shownin FIG. 2B, a characteristic line which can cover the designated bandalways exists. Therefore, it is sufficient to select the frequency rangecorresponding to the designated band on the basis of the actualcharacteristic found by measurement. It becomes unnecessary to adjustthe frequency, and it is unnecessary to preliminarily make the band tobe used and the switch state of the VCO correspond to each other in aone-to-one manner.

The variable frequency divider 12 includes: a prescaler 21 for dividingthe frequency of an oscillation signal of the VCO 10; and a modulocounter 22 constructed by a first counter 22N and a second counter 22Aeach for further dividing the frequency of the signal obtained by thefrequency division of the prescaler 21.

The frequency dividing methods of the prescaler 21 and the modulocounter 22 are according to known-techniques. The prescaler 21 isconstructed so that it can perform two kinds of frequency dividingoperations of different frequency division ratios such as 1/64 and 1/65which are switched by a count end signal of the second counter 22A. Thefirst and second counters 22N and 22A are programmable counters. In thefirst counter 22N, an integral part obtained by dividing a desiredfrequency (oscillation frequency fvco of the VCO desired to be obtainedas an output) by the frequency fref′ of the reference oscillation signalφref′ and by a first frequency ratio (64 in the embodiment) of theprescaler 21 is set. In the second counter 22A, the remainder (MOD) isset. After the set value is counted, the counting is finished, and theset value is counted again.

Concretely, for example, in the case where the frequency fref′ of thereference oscillation signal φref′ is 400 kHz and the oscillationfrequency fvco of the desired VCO is 3789.6 MHz, 3789.6÷0.4÷64=148 andthe remainder is 2. Consequently, the value N set in the first counter22N is “148” and the value A set in the second counter 22A is “2”. Whenthe prescaler 21 and the modulo counter 22 operate in a state where suchvalues are set, first, the prescaler 21 performs the 1/64 frequencydividing operation. When the second counter 22A counts the output of theprescaler 21 up to the set value of “2”, a count end signal MC is outputfrom the second counter 22A. By the signal MC, the operation of theprescaler 21 is switched, and the prescaler 21 performs the 1/65frequency dividing operation until the second counter 22A counts up tothe set value of “2” again.

By performing such operations, the modulo counter 22 can perform thefrequency dividing operation not at a ratio of an integer but at a radiohaving a decimal part. In the PLL circuit of the embodiment, feedback ismade so that the frequency of the output of the first counter 22Ncoincides with the frequency fref′ (400 kHz) of the referenceoscillation signal φref′ and the VCO 10 is oscillation-controlled.Consequently, in the concrete example in which the value N set in thefirst counter 22N is “148” and the value A set in the second counter 22Ais “2”, the oscillation frequency fvco of the VCO 10 is obtained by thefollowing equation and is 3789.6 MHz.fvco=(64×148+2)×fref′=9474×400=3789600

In practice, the first and second counters 22N and 22A take the form ofbinary counters, so that the value N set in the first counter 22N andthe value A set in the second counter 22A are given by binary codes. Inthe embodiment, although not limited, the first counter 22N operates asa 9-bit counter and the second counter 22A operates as a 6-bit counterat the time of the PLL operation. Therefore, the value set in the firstcounter 22N is given by nine bit codes N8 to N0, and the value set inthe second counter 22A is given by six bit codes A5 to A0.

Further, in the embodiment, the first counter 22N can operate as a11-bit counter at the time of measuring the frequency. The VCO 10 isconstructed so that the oscillation frequency can be switched in 16bands, that is, 16 stages. In the storing circuit 18, 16 registers RE0to REG15 for storing frequencies measured in the 16 bands are provided.The band determining circuit 19 has a comparator of 11 bits forcomparing values stored in the registers REG0 to REG15 of the storingcircuit 18 with the 9 bit codes of N8 to N0 set in the first counter 22Nand the upper two bits A5 and A4 in the 6 bit codes of A5 to A0 set inthe second counter 22A, and outputs a code of four bits VB3 to VB0 as aband switch signal to the VCO 10.

The control circuit 20 generates and outputs the switch signals VB3 toVB0 so as to sequentially select the 16 bands to the VCO 10 at the timeof measuring frequencies. Further, at the time of measuring frequencies,the control circuit 20 operates the first counter 22N as a 11-bitcounter and controls the first counter 22N so as to count clocks for aperiod of, not one cycle of the reference oscillation signal φref′, butfour cycles longer than that in the first embodiment. At the time ofmeasuring frequencies, the control circuit 20 stops the operation of thesecond counter 22A and controls so as not to switch the frequencydivision ratio of the prescaler 22. By the operations, at the time ofmeasuring frequencies, the prescaler 22 is controlled to perform thefrequency dividing operation of only 1/64.

In the embodiment, the reason why the counting operation is performedfor four cycles, not one cycle, of the reference oscillation signalφref′ at the time of measuring frequencies is to increase measurementprecision. Specifically, when it is assumed that the maximum erroroccurs in the counter 22N in measurement of one cycle of φref′, that is,one pulse count error occurs in the counter 22N in measurement in onecycle of φref′ for the reason that the prescaler 21 is provided, theerror at that time is increased by 64 times as the frequency divisionratio of the prescaler 21. Consequently, in the case where the referenceoscillation signal φref′ is 400 kHz, the maximum error of the counter22N is 25.6 MHz (=400 kHz×64). An error which occurs in the counter 22Nin measurement of four cycles is reduced to ¼ which is about 6.4 MHz.

The count values of 11 bits counted by the first counter 22N at the timeof frequency measurement are stored in any of the registers in thestoring circuit 18. In the PLL operation, the upper eight bits of thestored value are regarded as an integral part and compared with the setcodes N8 to N0 in the first counter 22N supplied from the outside in theband determining circuit 19. The lower two bits out of the values storedin the registers of the storing circuit 18 are regarded as a decimalpart, and compared with the upper two bits A5 and A4 out of the setcodes A5 to A0 in the second counter 22A supplied from the outside inthe band determining circuit 19. From a result of comparison between thestored values in the registers REG0 to REG15 of the storing circuit 18and the set codes N8 to N0 and A5 and A4, the use band of the VCO 10 isdetermined. Band switch codes VB3 to VB0 for selecting the band aregenerated and supplied to the VCO 10. In the VCO 10, in the case of thePLL circuit used in a communication system such as a GSM, the bands areset at intervals such as 400 kHz in accordance with channel intervals ofthe GSM.

The procedure of the frequency measuring operation by the controlcircuit 20 in the PLL circuit in the embodiment and the pull-inoperation of the PLL will be described by using the flowchart of FIG. 3.The frequency measurement is performed, for example, each time thesystem is turned on.

When the frequency measurement of the RF VCO starts, the control circuit20 first switches the switch SW0 to supply the direct-current voltageVDC to the loop filter 16 (step S1). The control circuit 20 waits untilthe voltage Vc of the loop filter 16 is stabilized and the oscillationfrequency of the VCO 10 becomes stable (step S2). Subsequently, thecontrol circuit 20 fixes the frequency dividing ratio of the prescaler21 to 1/64 and sets so that the first counter 22N operates as a 11-bitcounter (step S3). The control circuit 20 refers to a pointer indicativeof a selected band and outputs the codes VB3 to VB0 for selecting theband of the VCO 10 (step S4). The band selected first is, for example,BAND0 of which frequency range is the lowest.

Next, the control circuit 20 allows the first counter 22N to perform thecounting operation for four cycles of the reference oscillation signalφref′ (step S5). In step S6, the count value of the counter is storedinto a register in the storing circuit 18. The register to which thecount value is stored first is the first register REG0. After that, thecontrol circuit 20 determines whether the frequency measurement withrespect to all of the bands has been finished or not (step S7). If NO,the control circuit 20 adds one (+1) to the value of the pointerindicative of the selected band in step S8, returns to step S4, andrepeats the operations from step S4 to step S8. After the frequencymeasurement is finished on all of bands, the control circuit 20 advancesfrom step S7 to a standby mode in step S9, and finishes the frequencymeasurement.

After that, when a frequency set value according to the used channel issupplied from a baseband circuit in association with start oftransmission/reception in the standby mode, a band used in the VCO 10 isdetermined from a result of comparison between the values stored in theregisters RE0 to REG15 in the storing circuit 18 and the set codes N8 toN0, A5, and A4 on the basis of the frequency set value in the banddetermining circuit 19. A pull-in initial voltage is selected by thefollowing procedure in the pull-in initial voltage generating circuit 17(step S10).

Subsequently, the switch SW0 is switched by the control circuit 20, avoltage generated by the pull-in initial voltage generating circuit 17is applied to the loop filter 16, and pull-in is started (step S11). Atthe time when it is expected that a loop is stabilized after lapse ofpredetermined time since the pull-in was started, the control circuit 20switches the switch SW0 to connect the charge pump 15 and the loopfilter 16, thereby locking the PLL loop. After that, transmission andreception is started (step S12). The control circuit 20 has a timer TMRfor performing such time control. The timer TMR is constructed toperform a counting operation on the basis of, for example, the referenceoscillation signal φref from the reference oscillation circuit 11.

The pull-in initial voltage generating circuit 17 will now be described.

It is assumed that a set value corresponding to a frequency f(s) issupplied from the baseband circuit and the i-th band is selected from“n” (for example, 16) bands according to the set value. When the maximumfrequency is f(i:max) and the minimum frequency is f(i:min) in thecontrol voltage variable range of the band “i”, f(i:min)<f(s)<f(i:max).When the frequency band next lower than the selected band is i−1, themaximum frequency in the control voltage variable range of the band i−1is f(i−1:max) and the minimum frequency is expressed as f(i−1:min), andf(i:min)=f(i−1:max).

On the other hand, by setting the voltage of the loop filter 16 when thePLL circuit is locked at the maximum frequency f(i:max) as Vcp-max andsetting the voltage of the loop filter 16 when the PLL circuit is lockedat the minimum frequency f(i:min) as Vcp-min, a voltage Vcp-s of theloop filter 16 when the PLL circuit is locked at the set frequency f(s)can be obtained as follows from FIG. 4. It is assumed that, at the timeof the frequency measurement, measurement is executed at the maximumvoltage Vcp-max of the control voltage variable range, and a result ofthe measurement is stored in the registers REG0 to REG15 of the storingcircuit 18.

In this case, first, the maximum frequency f(i:max) of the band “i”selected according to the set frequency f(s) and the maximum frequencyf(i−1:max) of the band i−1 next lower than the band “i” are read fromthe storing circuit 18 and the frequency differenceΔfA=f(i:max)−f(i−1:max) is calculated. The differenceΔfB(=f(i:max)−f(s)) between the maximum frequency f(i:max) of theselected band “i” and the set frequency f(s) is calculated. By using thefrequency differences ΔfA and ΔfB, the voltage Vcp-s of the loop filter16 when the PLL loop is locked at the set frequency f(s) can beexpressed by the following equation.Vcp−s=Vcp−min+(Vcp−max−Vcp−min)×(1−ΔfB/ΔfA)

Therefore, by applying the voltage Vcp-s as the initial voltage VDCi tothe loop filter 16, the PLL can be pulled in at high speed. However, torealize a circuit of generating continuous voltages expressed by such anequation by a semiconductor integrated circuit device, a high-precisionDA converter is required. In the embodiment, consequently, the pull-ininitial voltage VDCi to be applied to the loop filter 16 is set step bystep in accordance with the frequency set value f(s). Concretely, asshown in FIG. 4, a circuit for generating divided voltages Vc1, Vc2, Vc3and Vcp-max obtained by dividing the control voltage variable range fromVcp−max to Vcp-min into M pieces (for example, four) is provided. Thevoltage closest to the filter voltage Vcp-s corresponding to thefrequency set value f(s) is selected and applied as the pull-in initialvoltage VDci to the loop filter 16.

FIG. 5 shows a concrete circuit example of the pull-in initial voltagegenerating circuit 17 in this case. The pull-in initial voltagegenerating circuit 17 in the embodiment includes: a resistive divider 71constructed by resistors R1 to R5 connected in series between a powersource voltage terminal Vcc and the ground point; a selector 72constructed by switches SW1 to SW4 for selecting any of voltagesgenerated by the resistive divider 71 and outputting the selectedvoltage; a computing circuit 73 for computing a voltage close to afilter voltage corresponding to the frequency set value f(s); and aconverting circuit 74 for decoding an output of the computing circuit 73and generating an on/off control signal for the switches SW1 to SW4 ofthe selector 72.

In the resistive divider 71, resistance values of the resistors R1 to R5are set so as to be able to generate the maximum control voltage Vcp-maxand divided voltages Vc1, Vc2, and Vc3. The reason why the minimumcontrol voltage Vcp−min is unnecessary is that, even when the band i−1next lower than the band “i” is selected and the maximum voltage Vcp−maxis applied in place of selecting the band “i” and applying the voltageVcp−min, the same result is obtained.

In the computing circuit 73, the pull-in initial voltage VDci iscalculated by the following arithmetic expression.VDci=Vcp−min+{(Vcp−max−Vcp−min)·M}×INT{(1−ΔfB·ΔfA)×M}

where “INT” denotes formation of an integer. Although rounding-off isdesirable as the formation of an integer, cut-off may be also used. Byemploying cut-off, the circuit can be simplified. Instead of calculatingthe pull-in initial voltage VDci by the arithmetic expression, it isalso possible to compute an integer value by INT{1−ΔfB·ΔfA}}×M andconvert the obtained value by the converting circuit 74 such as adecoder, thereby generating a control signal of the selector 72.

The case where the PLL circuit of the invention is applied to an RF ICas a component of a multiband radio communication system will now bedescribed. FIG. 6 shows an example of a detailed configuration of an RFIC and a schematic general configuration of a communication system.Although not limited, the system of the embodiment is a system of adirect conversion type.

Shown in FIG. 6 are an antenna 100 for transmitting/receiving signalwaves, an RF IC 200, a switch 10 for switching transmission/reception,an RF power amplifier 120 for amplifying a transmission signal, anoscillator (TXVCO) 130 for transmission, a loop filter 140 as acomponent of a PLL circuit on the transmission side, external circuitsand parts such as the reference oscillation circuit 11 and the loopfilter 16 constructing a PLL circuit for RF together with thehigh-frequency oscillator (RF VCO) 10 for generating an oscillationsignal of a frequency according to a desired band, a high-frequencyfilter 160 for removing unnecessary waves from a received signal, and abaseband circuit (LSI) 300 for converting transmission data to I and Qsignals and controlling the RF IC 200. The RF IC 200 is constructed as asemiconductor integrated circuit on a single semiconductor chip.

In the RF IC 200 of the embodiment, a transmission circuit isconstructed by: the RF VCO 10; a PLL component circuit 205 for RFincluding the frequency divider 13 phase comparator 14, charge pump 15,change-over switch SW0, prescaler 21, modulo counter 22, and the likewhich are shown in FIG. 1, for constructing a PLL circuit together withthe RF VCO 10, external reference oscillation circuit 11, and loopfilter 16; a band control circuit 206 constructed by the pull-in initialvoltage generating circuit 17, storing circuit 18, band determiningcircuit 19, and control circuit 20; an oscillation circuit (IF VCO) 210for generating an oscillation signal φIF of intermediate frequency suchas 320 MHz; a frequency divider 220 for generating a carrier wave suchas 80 MHz by dividing the oscillation signal φIF generated by theoscillation circuit 210; a modulator 230 for directly modulating thecarrier wave output from the frequency divider 220 by an I signal and aQ signal supplied from the baseband circuit 300; a frequency divider 250for dividing the frequency of an oscillation signal φRF supplied fromthe RF VCO 10; a mixer 260 for mixing a signal φRF′ obtained by thefrequency dividing operation of the frequency divider 250 with atransmission signal φTX fed back from the transmission oscillator(TXVCO) 130, thereby generating a signal φmix of a frequencycorresponding to a frequency difference of the two signals; a harmonicfilter 242 for cutting harmonic components leaked from the mixer 260; aphase detector 270 for detecting a phase difference between a signalfrom the mixer 260 and a modulated signal from the modulator 230; acharge pump 280 which is operated by a signal (UP, DOWN) output from thephase detector 270; a mode control circuit 290; and the like.

On the chip of the RF IC 200, circuits constructing a reception systemare provided, including: a low-noise amplifier 310 for amplifying areception signal; a demodulating circuit 320 for performing demodulationby combining a signal obtained by dividing the frequency of theoscillation signal φRF of the RF oscillator 10 by the frequency divider250 to the reception signal; and a programmable gain amplifier 330 foramplifying the demodulated signal and outputting the resultant signal tothe baseband circuit 300. Although not limited, an RF synthesizerconstructed by the external parts such as the reference oscillationcircuit 11 and the loop filter 16, and the RF VCO 10, PLL componentcircuit 205 for RF, and band control circuit 206 which are provided on achip is commonly used by the transmission-system circuits and thereception-system circuits.

A PLL circuit TxPLL for transmission for performing frequency conversionis constructed by the charge pump 280, phase detector 270, loop filter140, transmission oscillator (TX VCO) 130, and mixer 260. In themultiband radio communication system, the oscillation frequency φRF ofthe RF oscillator 10 is switched in accordance with a used band by, forexample, an instruction of the baseband circuit 300, thereby switchingthe transmission frequency.

The control circuit 290 is provided with a control register CRG. In theregister CRG, setting is made on the basis of a signal from the basebandcircuit 300. Concretely, a clock signal CLK for synchronization, a datasignal SDATA, and a load enable signal LEN as a control signal aresupplied from the baseband circuit 300 to the RF IC 200. When the loadenable signal LEN is asserted to the effective level, the mode controlcircuit 290 sequentially receives the data signals SDATA transmittedfrom the baseband circuit 300 synchronously with the clock signals CLKand sets the data signals SDATA into the control register CRG. Althoughnot particularly limited, the data signals SDATA are transmitted inseries. The baseband circuit 300 is constructed by a microprocessor andthe like.

The control register CRG has, although not particularly limited, acontrol bit for starting frequency measurement of the RF VCO 10 in theforegoing embodiment, a bit for designating a mode such as a receptionmode, a transmission mode, a standby mode or sleep state in which only apart of circuits operates and circuits in the most part including atleast the oscillation circuit stop at the time of waiting or the like,and a warm-up mode for starting the PLL circuit, and a bit fordesignating a pull-in mode of the PLL circuit TxPLL for transmission.

Table 1 shows an example of setting of the frequencies of theoscillation signals φIF, φTX and φRF of the oscillator (IFVCO) 210 forintermediate frequency, oscillator (TXVCO) 130 for transmission, andoscillator (RFVCO) 10 for high frequency in the RF IC for triple bandsof the embodiment. TABLE 1 IFVCO TXIF TXVCO RXVCO (MHz) (MHz) (MHz)(MHz) reception transmission GSM900 640 80 880 3700 3840 640 80 915 38403980 DCS1800 640 80 1710 3610 3580 640 80 1785 3760 3730 PCS1900 640 801850 3860 3860 640 80 1910 3980 3980

As shown in Table 1, in the embodiment, the oscillation frequency of theoscillator (IF VCO) 210 for intermediate frequency is set to 640 MHz inany of the cases of GSM, DCS, and PCS, which is divided into ⅛ by thefrequency divider 220, thereby generating a carrier wave TXIF of 80 MHz.In such a manner, modulation is performed.

On the other hand, the oscillation frequency of the RF oscillator (RFVCO) 10 is set to 3840 to 3980 MHz in the case of the GSM, 3580 to 3730MHz in the case of DCS, and 3860 to 3980 MHz in the case of the PCS. Bythe frequency divider 250, in the case of the GSM, the oscillationfrequency is divided into ¼ and, in the case of the DSC and PCS, theoscillation frequency is divided into ½. The resultant signal issupplied as φRF′ to the mixer 260. From the mixer 260, a signalcorresponding to the difference (FRF−FTX) between φRF′ and the frequencyof the transmission oscillation signal φTX from the oscillation circuit130 for transmission is output. The transmission PLL (TxPLL) operates sothat the difference signal and the frequency FTXIF of the modulationsignal coincide with each other.

In the embodiment of FIG. 6, the case where the PLL circuit of theinvention is applied as a PLL circuit for RF for generating an RF signal(high frequency signal) to be mixed with a reception signal in the mixer260 is shown. Alternately, the PLL circuit of the invention may beapplied as a PLL circuit for IF for generating an IF (intermediatefrequency) signal to be mixed with a transmission signal by a mixer.Although not shown, the PLL circuit of the invention can be also appliedas a PLL circuit for transmission for generating a transmission signalin an RF IC of a direct up-conversion method for modulating atransmission signal directly by an I signal and a Q signal from thebaseband circuit 300.

An embodiment of applying the PLL circuit of the invention to an RF ICin a radio communication system of a polar loop type will now bedescribed by referring to FIG. 7.

Shown in FIG. 7 are the power module 120 including an RF power amplifier121 for driving the antenna 100 and performing transmission and acoupler 122 for detecting a transmission power, an RF IC 200 capable ofperforming GMSK modulation in a GSM system and 8-PSK modulation in anEDGE system, a baseband circuit 300 for generating I and Q signals onthe basis of transmission data (baseband signal) and generating acontrol signal for the RF IC 200 and a bias voltage VBIVGAS to the poweramplifier 121 in the power module 120, an oscillator TxVCO fortransmission for generating a phase-modulated transmission signal(carrier wave), and a loop filter LPF1 for regulating the band of aphase control loop.

Each of the RF IC 200 and the baseband LSI 300 is constructed as asemiconductor integrated circuit on a single semiconductor chip. On thechip of the RF IC 200, not only circuits of a transmission system butalso a reception system circuit 410 including a low noise amplifier(LNA), a mixer (Rx−MIX) for down-converting a reception signal to asignal of an intermediate frequency, and a programmable gain amplifier(PGA) of high gain is formed.

The polar loop type radio communication system of the embodiment has twocontrol loops of not only a feedback loop for phase control(hereinbelow, called a phase loop) but also a feedback loop foramplification control (hereinbelow, called an amplitude loop).

The RF IC 200 as a component of the polar loop of the embodimentincludes: the oscillator (RF VCO) 10 for generating the oscillationsignal φRF of high frequency; the oscillator (IF VCO) 210 for generatingthe oscillation signal φIF of intermediate frequency; the phasefrequency divider 220 for generating a signal of which phase is shiftedfrom the phase of the oscillation signal φIF generated by the IF VCO 210by 90°; the quadrature modulator 230 for performing quadraturemodulation by mixing the I and Q signals supplied from the baseband LSI300 with a signal obtained by frequency division by the phase frequencydivider 220; the mixer 260 for mixing a feedback signal from theoscillator TxVCO for transmission with the oscillation signal φRF fromthe RF VCO 10 to perform down-conversion to a signal of 80 MHz or thelike; the phase detector 270 for detecting a phase difference between anoutput signal of the mixer 260 and an output signal of the quadraturemodulator 120; a mixer 132 for mixing a signal from the coupler 122 fordetecting an output level of the power amplifier 121 and the oscillationsignal φRF from the RF VCO 10; a feedback-side variable gain amplifierMVGA for amplifying an output of the mixer 132; an amplitude detector450 for comparing the amplified signal and an output signal of thequadrature modulator 230 to detect an amplitude difference; a loopfilter LPF2 for generating a voltage according to an output of theamplitude detector 450 and regulating a frequency band of the amplitudeloop; a forward-side variable gain amplifier IVGA for amplifying anoutput of the loop filter LPF2; a gain controller 460 for controllingthe gains of the variable gain amplifiers MVGA and IVGA; a register 470for setting control information, an operation mode, and the like in thechip; and a sequencer 480 for outputting timing signals to circuits inthe chip on the basis of the set value in the register 470 and operatingthe circuits in a predetermined order in accordance with an operationmode.

The RF IC 200 of the embodiment has, in correspondence with the RF VCO10: the PLL component circuit 205 for RF including the frequency divider13 phase comparator 14, charge pump 15, change-over switch SW0,prescaler 21, and modulo counter 22 shown in FIG. 1 and constructing aPLL circuit together with the RF VCO 10, external reference oscillationcircuit 11, and loop filter 16; and the band control circuit 206including the pull-in initial voltage generating circuit 17 storingcircuit 18 band determining circuit 19 and control circuit 20. With theconfiguration, automatic selection of the optimum band and pull-in ofthe PLL circuit on start of transmission/reception can be performed athigh speed. The reference oscillation circuit 11 for generating areference oscillation signal takes the form of an external part.

In the embodiment, the amplitude loop is constructed by the coupler 122,mixer 132, variable gain amplifier MVGA, amplitude detector 450, loopfilter LPF2, variable gain amplifier IVGA, and power amplifier 121. Thephase loop is constructed by the phase detector 270, loop filter LPF1,oscillator TxVCO for transmission, mixer 260, and phase detector 270. Inthe phase loop, if a phase difference occurs between the output signalof the quadrature modulator 30 and the feedback signal from the mixer260, a voltage to decrease the error is supplied to a frequency controlterminal of the oscillator TxVCO for transmission, and the phase of afeedback signal from the mixer 260 come to coincide with the phase ofthe output signal of the quadrature modulator 230. By the phase loop, acontrol to prevent the phase of the output of the oscillator TxVCO fortransmission from being shifted due to fluctuations in power voltage andchanges in temperature is performed. The amplitude of the oscillationTxVCO for transmission is constant.

Further, in the embodiment, a change-over switch SW10 for feeding backan output of the variable gain amplifier MVGA to the phase detector 270to make a path of the coupler 122, mixer 132, and variable gainamplifier MVGA a feedback path commonly used by the amplitude loop andthe phase loop is provided. The switch SW10 is switched by the sequencer480 in accordance with a set state to the register 470 from the basebandLSI 300.

In the EDGE mode, both a phase modulation component and an amplitudemodulation component are included in an output of the power amplifier120. Consequently, an output of the oscillator TxVCO for transmission oran output of the power amplifier 121 may be used as a feedback signal tothe phase detector 270 having a phase component on the output side.However, at start of transmission, an output of the power amplifier 121is not high yet, so that the phase loop cannot be locked by the feedbacksignal from the amplitude loop. On the other hand, in the EDGEmodulation mode, a feedback bus of the amplitude loop is indispensable,so that after the loop is locked, the amplitude loop may be shared andthe phase loop in a narrow sense including the mixer 260 may beinterrupted. It produces advantages such that power consumption can bereduced and phase modulation can be performed with higher precision. Inthe embodiment, at the rise of an output, the switch SW10 is switched tothe side of selecting a feedback signal from the phase loop. After theloop is stabilized, the switch SW10 is switched to the side of selectinga feedback signal from the amplitude loop.

The loop filter LPF1 on the phase loop is constructed by capacitors C0and C1 and a resistor R1 connected to the capacitor C1 in series. Thevalues of capacitors and resistor are determined so that the frequencyband of the loop filter LPF1 becomes a frequency band of 1.2 MHz or thelike in which the degree of noise suppression is high in considerationof the GMSK modulation mode of performing only phase modulation.

In the transmission circuit of the embodiment, in the case of operatingin an 8-PSK modulation mode, in the amplitude loop, an output of thepower amplifier 120 is detected by the coupler 122, a detection signalis converted by the mixer 132 to an intermediate frequency band (IF),the resultant is amplified by the variable gain amplifier MVGA, and theamplified signal is supplied as a feedback signal SFB to the amplitudedetector 450. The transmission signal modulated by the quadraturemodulator 230 and the feedback signal SFB are compared with each otherby the amplitude detector 450 to thereby detect an amplitude difference.The amplitude difference is amplified by the variable gain amplifierMVGA, the resultant is applied as a control voltage VAPC to the outputcontrol terminal of the power amplifier 210, and the amplitude controlis performed.

In the embodiment, the power amplifier 121 is constructed by an FET orthe like. To the drain terminal or source terminal of the FET, a drivevoltage (Vdd) according to the control voltage VAPC is generated andapplied by a voltage control circuit (not shown) provided for the powermodule 120. To the gate terminal of the power FET, a proper bias voltageVBIAS generated by a not-shown bias circuit is applied.

The gain control for the variable gain amplifier IVGA on the forwardpath and the variable gain amplifier MVGA on the feedback path will nowbe described.

In a portable telephone terminal conformed with EDGE or GSM, a powercontrol for increasing or decreasing an output power POUT of the poweramplifier to a desired value within predetermined time is performed. Ina polar loop, the power control is executed by controlling the gain ofthe variable gain amplifier MVGA. Concretely, by decreasing the gain ofthe variable gain amplifier MVGA, the feedback signal of the amplitudeloop is decreased. To make the feedback signal match with a referencesignal from the modulator, the power amplifier is controlled so that thegain GPA(POUT/PIN) increases, and the output power POUT increases. Todecrease the output power POUT, it is sufficient to decrease the gain ofthe variable gain amplifier MVGA. In the embodiment, the gain control ofthe variable gain amplifier MVGA is executed by a control voltage VRAMPfrom the baseband LSI 300. Moreover, the ratio of decrease or increaseof the gain GMVGA of the variable gain amplifier MVGA and the ratio ofincrease or decrease of the gain GPA of the power amplifier are set tobe always equal to each other.

Consequently, a change in the gain of the variable gain amplifier MVGAwith respect to the control voltage VRAMP is expressed by a straightline which slants to the right. A change in the gain of the poweramplifier 120 with respect to the control voltage VRAMP is expressed bya straight line which rises to the right. The output power POUT of thepower amplifier 120 increases linearly with respect to the controlvoltage VRAMP. As described above, to control the output power POUT ofthe power amplifier 120 linearly in unit of dB by the control voltageVRMP is valid to stably operate the amplitude loop.

On the other hand, a reference signal from the modulator 230 is a signalmodulated by the 8-PSK. Although an amplitude component changes, acontrol is executed so that the amplitude component of the output powerPOUT of the power amplifier coincides with the reference signal SREF bythe action of the amplitude control loop. The output power POUT of thepower amplifier 120 is maintained at a desired value by the powercontrol. In the polar loop as described above, a desired output powercan be maintained without exerting an influence on the amplitudecomponent modulated by the 8-PSK.

Although the invention achieved by the inventors et al. has beenconcretely described on the basis of the embodiments, the invention isnot limited to the embodiments. For example, a case where the divisionnumber M of the control voltage is “4” in the PLL circuit of theembodiment has been described. The division number is not limited to “4”but may be “5” or “6”. The larger the division number is, the more thepull-in time can be shortened by accurately setting the pull-in initialvoltage VDci. When the division number is too large, however, thecircuit scale of the pull-in voltage generating circuit 17 becomes largeand timer control of pull-in time becomes complicated. Consequently,according to a circuit format, when the division number is set to be toolarge, there is a case that a demerit exceeds a merit.

Although the frequency of the VCO 10 measured by using a predetermineddirect current voltage (Vcp-max in the embodiment) is stored in thestoring circuit 18 and the pull-in initial voltage is selected on thebasis of the frequency information read from the storing circuit 18 anddesignated frequency information from the baseband circuit at start ofthe operation of the PLL circuit. Alternately, it is also possible tomeasure the frequency of the VCO 10 by using a plurality ofdirect-current voltages (Vcp-max, Vc3, Vc2, Vc1, and the like in FIG.4), store the measured frequencies in the storing circuit 18 and, atstart of the operation of the PLL circuit, and select the pull-ininitial voltage on the basis of the frequency information read from thestoring circuit 18 to determine the use band by the band determiningcircuit 19.

Further, in the embodiment, the storing circuit 18 for storing thepre-measured frequency of the VCO 10 and the band determining circuit 19for determining the use band of the VCO 10 are provided in the RF IC. Itis also possible to omit the band determining circuit 19 and provideonly the storing circuit 18 in the RF IC. At start of operation of thePLL circuit, the baseband circuit 300 reads out the frequencyinformation from the storing circuit 18 and determine a use band of theVCO 10. A signal for controlling the selector 72 in the pull-in initialvoltage generating circuit 17 may be supplied together with the bandswitch codes VB3 to VB0. Further, in the embodiment, the direct-currentvoltage VDC at the time of frequency measurement is applied from thevoltage generating circuit 17 to the VCO 10 via the loop filter 16. TheVCO control voltage Vc may be directly applied from the voltagegenerating circuit 17 to the VCO 10.

The case where the invention achieved mainly by the inventors herein isapplied to the PLL circuit used for the radio communication system of aportable telephone in the field of utilization as a background of theinvention has been described. The invention is not limited to the casebut can be also applied to a semiconductor integrated circuit having aPLL circuit, particularly, a semiconductor integrated circuit having aPLL circuit in which a variable frequency range of the VCO is wide.

Effects produced by representative inventions in the inventionsdisclosed in the application will be briefly described as follows.

According to the invention, an initial voltage which is extremely closeto a control voltage applied when an oscillation circuit oscillates at adesired frequency on start of oscillating operation can be applied.Consequently, it is unnecessary to provide a current source for pull-inof the PLL and, moreover, the communication semiconductor integratedcircuit device having a PLL circuit capable of performing pull-inaccurately at high speed can be realized. Further, in a radiocommunication system using the communication semiconductor integratedcircuit device of the invention, communications by signals in aplurality of frequency bands are possible. Moreover, the VCO can beformed on a single semiconductor chip together with a modem or the like.Thus, the number of components constructing the system can be reducedand the miniaturization of the device can be achieved.

1-22. (canceled)
 23. A semiconductor integrated circuit device for aradio communication device comprising: a phase locked loop circuit whichincludes a phase detection circuit which detects a phase differencebetween a reference signal having a predetermined frequency and afeedback signal which is an output signal of the phase locked loopcircuit, a signal generation circuit which generates a first voltage inresponse to phase difference information signals from the phasedetection circuit, an oscillation circuit which generates the outputsignal responding to a voltage of a filter that is charged or dischargedby the signal generation circuit and which generates the output signalin accordance with desired frequency information; a measuring circuitwhich measures a frequency of the output signal and outputs firstfrequency information which includes the frequency of the output signal;a band selection circuit which selects an oscillation frequency bandfrom a plurality of frequency bands by comparing the desired frequencyinformation and the first frequency information and which generates aband selection signal; an initial voltage generating circuit whichgenerates a second voltage based on the band selection signal; and aswitching circuit which elects the second voltage or the first voltagefor supplying to the filter or the oscillation circuit, wherein theswitching circuit elects the second voltage at a beginning of operationof the phase locked loop circuit to perform a pull-in operation, and theswitching circuit is switched to supply the first voltage to theoscillation circuit or the filter to lock the phase locked loop circuitafter the pull-in operation.
 24. A semiconductor integrated circuitdevice for a radio communication device according to claim 23, whereinthe second voltage is composed of a plurality of voltages and set stepby step, and wherein the initial voltage generating circuit selects oneof the plurality of voltages as the second voltage for the oscillationcircuit to oscillate with a desired frequency.
 25. A semiconductorintegrated circuit device for a radio communication device according toclaim 23, wherein the second voltage is supplied to the filter or theoscillation circuit when the measuring circuit measures the frequency ofthe output signal.
 26. A semiconductor integrated circuit device for aradio communication device according to claim 23, further comprising acontrol circuit which controls switching of the switching circuit,wherein at a time that the phase locked loop circuit is in an open loopstate, the switching circuit is switched by the control circuit forsupplying the second voltage to the oscillation circuit or the filter,so that the oscillation circuit is oscillated in accordance with thesecond voltage, and the measuring circuit measures the frequency in eachof the oscillation frequency bands, and wherein at a time that the phaselocked loop circuit is a closed loop state, the switching circuit isswitched by the control circuit for supplying the first voltage to theoscillation circuit or the filter, so that the oscillation circuit isoscillated at the desired frequency in accordance with the desiredfrequency information.
 27. A semiconductor integrated circuit device fora radio communication device according to claim 26, further comprising acounter circuit which divides the frequency of the output signal andwhich is provided between the oscillation circuit and the phasedetection circuit, wherein the counter circuit also performs as themeasuring circuit.
 28. A semiconductor integrated circuit device for aradio communication device according to claim 27, wherein the countercircuit includes: a frequency divider capable of switching a frequencydivision ratio; a first programmable counter capable of computing avalue corresponding to a quotient obtained by dividing a frequency of asignal to be output from the oscillation circuit by a frequency of thereference signal and further dividing the resultant by one of pluralfrequency division ratios of the frequency divider; and a secondprogrammable counter capable of computing a value corresponding to aremainder of the division, wherein the value computed by the firstprogrammable counter is supplied to the band selection circuit as thefirst frequency information.
 29. A semiconductor integrated circuitdevice for a radio communication device according to claim 23, furthercomprising: a first mixer for mixing the output signal from the phaselocked loop circuit or a signal obtained by dividing the frequency ofthe output signal with a reception signal, thereby obtaining ademodulated signal; and a second mixer for mixing the output signal fromthe phase locked loop circuit or a signal obtained by dividing thefrequency of the output signal with a transmission signal, therebyobtaining a signal of a frequency corresponding to a frequencydifference.
 30. A semiconductor integrated circuit device for a radiocommunication device according to claim 29, further comprising a thirdmixer for mixing the output signal from the phase locked loop circuitwith a detection signal of the power amplifier, thereby obtaining afrequency-converted signal.